The present invention relates generally to circuitry for minimizing dc offset variations in an analog signal, and more specifically to circuitry for minimizing such variations in an analog signal defined by an ac signal component due to a driving force and a dc offset signal component independent of the driving force.
Airbag systems are commonly used in automotive applications to provide protection for the vehicle operator and/or passenger in the event of a vehicular collision. One known technique for implementing an airbag system includes detecting vehicular acceleration via an accelerometer and then evaluating the resulting acceleration signal to determine whether an impact of sufficient severity has occurred to require the airbag to deploy.
Accelerometers may be formed in accordance with a variety of known techniques, and an increasingly popular accelerometer used in automotive airbag systems comprises a piezoresistive sensor, typically micro-machined, whose differential analog output voltage (VDIFF) is proportional to the applied acceleration. The differential output, VDIFF, is typically represented by the following equation:
VDIFF=(S*gxc2x1VOFF)xe2x80x83xe2x80x83(1),
where S is the sensitivity of the sensor (typically in units or uV/g or mV/g), g is the applied acceleration (or deceleration), and VOFF is an offset voltage of the sensor that is independent of applied acceleration (or deceleration). The differential output voltage of accelerometers typically used in automotive airbag applications thus provide an analog acceleration signal defined by an ac signal component due to the driving force (acceleration/deceleration) and a dc offset signal component independent of the driving force. The sensitivity term, S, and offset term, VOFF, of equation (1) are typically dependent upon temperature, fabrication process variations, physical stress due to packaging and mounting of the sensor, and other factors.
Most applications which use accelerometers include signal conditioning circuitry for amplifying the analog acceleration signal and to compensate for sensitivity and dc offset variations. One drawback associated with such signal conditioning circuitry is the need for cancellation of the dc offset term, VOFF. Although VOFF may be minimized at the input of such signal conditioning circuitry to thereby minimize temperature dependent effects on VOFF due to the signal conditioning circuitry, any residual offset voltage, VOFF, is multiplied by the gain of the signal conditioning circuitry. With the high gains typically associated with such signal conditioning circuitry, the resulting temperature-dependent dc offset voltage, VOFF, may vary to unacceptable levels over the operating temperature range. For example, typical accelerometer-based airbag systems require dc offset errors of less than 20 mV over an operating temperature range of between xe2x88x9240xc2x0 C. and +125xc2x0 C. With a typical signal conditioning circuitry gain of 200, variations in VOFF, due to temperature dependency alone, must be less than approximately 0.6 micro volts/T(xc2x0 C.) to meet the 20 mV offset error over the entire temperature range.
Variations in VOFF typically change very slowly in comparison with impact data capture rates of most airbag systems. As such, it is desirable to compensate for such slow variations with a correspondingly slowly changing compensation technique. Since most applications which use accelerometers also include a microprocessor to process the acceleration signal, a popular technique for compensating the slowly varying DC offset signal, VOFF, is to implement a software algorithm executable by the microprocessor to provide a long time constant xe2x80x9csoftwarexe2x80x9d filter. The dominant error in such a filter is the quantization noise of the analog-to-digital (A/D) converter, which is typically 20 mV for an 8 bit 5 volt application.
Although such microprocessor-based airbag systems have been used extensively, they have a number of drawbacks. First, such a system is designed around a process optimized for digital circuits. These requirements are inconsistent with the requirements for processing analog signals such as those provided by an analog accelerometer. Second, microprocessors are typically large and complicated integrated circuits, resulting in significant cost and area penalties for the circuit and system designers. Finally, the finite resolution of typical A/D converters in such systems introduces error into the algorithm, as previously discussed, which may be unacceptable for some applications.
To avoid the foregoing drawbacks of a microprocessor-based acceleration signal evaluating system, it is desirable to implement an analog signal processing system for evaluating the analog acceleration signal. An example of one such system is described in U.S. patent application Ser. No. 08/610,021, and entitled xe2x80x9cAnalog Signal Processing System for Determining Airbag Deploymentxe2x80x9d, which is assigned to the assignee of the present invention, and which patent application is herein incorporated by reference. However, such an analog signal processing system may not rely upon an easily implemented software algorithm to provide a long time constant filter, and must therefore provide other means for generating the long time constant filter. Preferably, the signal conditioning circuitry, analog signal processing system, and the long time constant filter are provided on a single integrated circuit which does not require costly external components for operation thereof.
To minimize variations in the dc offset component of an analog acceleration evaluating system, a number of known analog techniques have been implemented. For example, referring to FIG. 1, analog acceleration signal conditioning circuitry 10 is provided which is operable to minimize VOFF (equation (1)), prior to signal conditioning by the signal conditioning circuitry. System 10 includes an acceleration sensor 12 connected to a signal conditioner 14 via signal paths 16 and 18. Signal path 16 carries a first acceleration signal S+, and signal path 18 carries a second acceleration signal Sxe2x88x92, wherein the differential input VIN to signal conditioner 14 is defined as VIN=(S+xe2x88x92Sxe2x88x92). Referring to equation (1), VIN=VDIFF. The signal conditioner 14 provides a transfer function equal to [(1/RIN)*AV(T)]. An output 20 of signal conditioner 14 thus provides a signal VIN, nominally increased by some gain factor AV, divided by an input resistance RIN. The AV term not only provides gain for the input signal, but also includes a temperature dependency to compensate for the temperature dependency of equation (1). The output 20 of signal conditioner 14 is connected to an inverting input 22 of a first amplifier 24 via signal path 26. An output 30 of amplifier 24 is connected to one end of a resistor R2 32, the opposite end of which is connected to signal path 26. A non-inverting input 28 of amplifier 24 is connected to a mid-supply voltage VMID.
Signal path 26 is further connected to a XY/Z input 34 of offset compensation circuit 36 via signal path 38. A first current source ID 40 provides current from a voltage source VS to an X input 42 of offset compensation circuit 36. A second current source ID 41 provides current from voltage source VS to XY/Z input 34 of offset compensation circuit 36. One end of a resistor R1 44 is connected to a Y input 48 of offset compensation circuit 36, which input is further connected to a first current source IE 45 operable to draw current out of offset compensation circuit 36. The opposite end of resistor R1 44 is connected to a temperature dependent voltage source V(T) 46. A second current source IE 50 is connected to a Z input 52 of offset compensation circuit 36, and is configured to draw current out of offset compensation circuit 36. The current IA flowing through signal path 38 is defined by the equation:
IA=(ID*V(T))/(IE*R1)xe2x80x83xe2x80x83(2)
The output 30 of amplifier 24 is further connected to one end of a resistor R2 54, the opposite end of which is connected to an inverting input 56 of a second amplifier 58 via signal path 60. A non-inverting input 62 of amplifier 58 is connected to VMID. An output 64 of amplifier 58 is connected to one end of a variable resistor R3 66, the opposite end of which is connected to signal path 60. Also connected to signal path 60 is a current source 68 operable to draw a current IF away from signal path 60. The output 64 of amplifier 58 provides the output signal VOUT 70 from the analog signal conditioning circuitry 10. The overall circuit response is represented by the following equation:
VOUT=[((VIN/RIN)*AV(T))+IFxe2x88x92(ID*V(T))/(IE*R1)]*R3+VMID(1+R3/R2)xe2x80x83xe2x80x83(3)
The circuitry 10 is adjusted for operation by first adjusting the value of R3 66 to provide a desired sensitivity gain. Thereafter at room temperature, temperature-dependent voltage V(T) is adjusted to VMID. Also at room temperature, any undesirable offset component is also canceled by adjusting IF 68. Because V(T) has been set to VMID, the offset compensation circuit 36 has no effect on room temperature operation of circuity 10. Circuitry 10 is then taken to a different temperature, and the current IE 50 is adjusted with respect to current ID 40 so that the temperature dependence of the dc offset component VOFF (equation (1)) is minimized at the input 22 to amplifier 24. Circuitry 10 of FIG. 1 is further described in U.S. patent application Ser. No. 08/421,956, filed Apr. 14, 1995, by Koglin, et al., and entitled xe2x80x9cProgrammable Transducer Amplifier Circuitxe2x80x9d, which is assigned to the assignee of the present invention, and which patent application is herein incorporated by reference.
In circuitry 10 of FIG. 1, the dc offset component, VOFF, of equation (1), is canceled at the input of the amplification stage. However, since typical gains of such amplification circuits are 100 or greater, any slight error in VOFF at the input is multiplied by this amount. Such circuits, by themselves, may typically guarantee dc offset 15 variations within the range of +/xe2x88x92 300 mV over the operating temperature range. However, output 70 is typically connected to a microprocessor which cancels the remaining offset with a software filter to provide an acceleration signal having less than 20 mV of dc offset error, as may be required by an acceleration signal evaluating system. Circuitry 10 of FIG. 1, although it implements one known form of dc offset cancellation, it is not typically used without a microprocessor-based software filter. Circuitry 10 is insufficient to achieve an effective 20 mV offset error, by itself, in a strictly analog signal processing system.
Referring to FIG. 2, another known technique for canceling VOFF of equation (1) is shown. Circuitry 100 of FIG. 2 includes an analog sensor 102 connected to one end of a capacitor C1 104 via signal path 106, the opposite end of which is connected to an input 108 of gain stage 110. Input 108 is further connected to one end of a resistor R1 112, the opposite end of which is connected to a voltage supply 114, preferably set at VMID. Sensor 102 is further connected to one end of a second capacitor C2 116 via signal path 118, the opposite end of which is connected to a second input 120 of gain stage 110. One end of a second resistor R2 122 is connected to input 120 of gain stage 110, the opposite end of which is connected to VMID. An output 124 of gain stage 110 provides the amplified acceleration signal VOUT.
In operation, capacitors C1 104 and C2 116, in conjunction with resistors R1 112 and R2 122, form a high pass filter operable to pass high frequency acceleration signals to the gain stage 110, yet block low frequency, or near-dc variations. Although circuitry 100 of FIG. 2 is effective to cancel VOFF of sensor 102, it has a number of limitations.
First, only the dc offset component, VOFF, of sensor 102 is canceled. Any offset in gain stage 110 is thereby unaffected. Typical offsets at the input of a gain stage, such as gain stage 110, are in the range of 1-2 mV, and may be as much as 10 mV in MOS circuits. With gains of greater than 100, output offsets will therefore be in excess of 200 mV, which is unacceptable in a strictly analog acceleration signal processing system. Second, a long time constant of the high pass filter requires large values of R and C. In integrated circuitry, large values of R are extremely area intensive, and large C values can only be realized with external components. Use of such external componentry is both bulky and expensive. Finally, the high pass filter arrangement of circuitry 100 introduces a large impedance at the input of gain stage 110, which large input impedance amplifies the effects of any leakage current. Typical leakage currents specified on capacitors and between pins on printed circuit boards are in the range of 1 uA, and the input impedance of the high pass filter arrangement of circuitry 100 must be in the range of a megaohm or more to achieve the desired input high pass filter time constant with reasonable capacitor values. This combination of input impedance and leakage capacitance may generate more than 1 volt of offset at the input, which is far too great for the desired application.
Referring now to FIG. 3, yet another known technique for canceling VOFF of equation (1) is shown. Signal conditioning circuitry 150 of FIG. 3 utilizes a known feedback integrator to generate a high pass filter with a long time constant. Circuitry 150 includes an analog sensor 152 connected to one input 154 of gain stage 156 via signal path 158, and to a second input 160 of gain stage 156 via signal path 162. An output 164 of gain stage 156 is connected to one end of a resistor RF 166 via signal path 168. The opposite end of resistor RF 166 is connected to an inverting input 170 of amplifier 172 via signal path 174. A non-inverting input 176 is connected to mid-supply voltage VMID. An output 178 of amplifier 172 is connected to one end of a feedback capacitor CF 180, the opposite end of which is connected to signal path 174. The output 178 of amplifier 172 is further connected to an input 182 of gain stage 156 via signal path 184. Output 164 of gain stage 156 is further provided as the analog output signal VOUT 186 of circuit 150.
The overall transfer response of circuitry 150 is represented by the following equation:
VOUT=AV/[1+AV/(jw*RF*CF)]+VMIDxe2x80x83xe2x80x83(4),
where AV is the gain of gain stage 156, and w is the frequency of the applied signal in radians. Those skilled in the art will recognize that equation (4) represents a typical transfer response of a high pass filter.
Circuitry 150 is advantageous over circuitry 100 of FIG. 2 in that it effectively cancels the dc offset component of both the sensor 152 and the gain stage 156, as well as only requiring one external component (the capacitor CF) in an integrated circuit arrangement. One drawback to circuitry 150 of FIG. 3, like circuitry 100 of FIG. 2, is that it still requires a large external capacitor, CF, and a large on-chip resistor, RF, to realize the long time constant of the high pass filter. Due to high leakage currents associated with such external capacitors, the high-valued RF (typically about one megaohm) required by circuitry 150 results in excessively high voltage offsets at VOUT 186.
It is apparent that the foregoing prior art dc offset compensation circuits are insufficient to provide a completely integrated means for minimizing variations in VOFF of equation (1) in a strictly analog signal processing system. What is therefore needed is circuitry for minimizing variations in VOFF of equation (1), as well as minimizing variations in any dc offset attributable to the signal gain stage, which is easily integrated into a single integrated circuit, and which is capable of generating a long time constant filter while eliminating the need for any bulky and expensive external componentry.
The foregoing shortcomings of the prior art are addressed by the present invention. In accordance with one aspect of the present invention, analog signal conditioning circuitry comprises an amplifier having a first input receiving an analog input signal defined by an ac signal component due to a driving force and a dc offset signal component independent of the driving force, a second input receiving a reference signal and an output providing an analog output signal defined by an amplified representation of the analog input signal and a dc offset component corresponding to the reference signal, a low pass filter having an input connected to the amplifier output and an output providing a low frequency representation of the analog output signal, and a feedback circuit having a periodic clock signal associated therewith, a first input connected to the low pass filter output, a second input receiving the reference signal, and an output connected to the first input of the amplifier for providing an analog feedback signal thereto. The feedback circuit incrementally increases the analog feedback signal each clock cycle that the low frequency analog output signal exceeds the reference signal and incrementally decreases the analog feedback signal each clock cycle that the reference signal exceeds the low frequency analog output signal. The analog feedback signal compensates for variations in the dc offset component of the analog input signal to thereby maintain the dc offset component of the analog output signal within a predefined range of the reference signal.
In accordance with another aspect of the present invention, feedback circuitry for minimizing dc offset variations in an analog output signal of a gain circuit having an input receiving an analog input signal defined by an ac signal component due to a driving force and a dc offset component independent of the driving force, comprises a comparator having a first input receiving the analog output signal, a second input receiving a reference signal corresponding to a desired dc offset component of the analog output signal, and an output, a counter circuit having a count value associated therewith, a first input connected to the comparator output and a plurality of counter outputs. The counter circuit periodically changes the count value in a first direction when the analog output signal exceeds the reference signal and periodically changes the count value in a second opposite direction when the reference signal exceeds the analog output signal. The counter circuit provides digital output signals at the plurality of counter outputs corresponding to the count value. A signal converter is also provided and has a corresponding plurality of inputs connected to the plurality of counter outputs and an output connected to the input of the gain circuit. The signal converter circuit converts the plurality of digital output signals to an analog feedback signal and provides the analog feedback signal to the converter circuit output, wherein the analog feedback signal minimizes variations in the dc offset component of the analog output signal by compensating for variations in the dc offset component of the analog input signal.
In accordance with a further aspect of the present invention, an analog signal amplifier circuit having a first input receiving an analog input signal defined by an ac signal component due to a driving force and a dc offset component independent of the driving force, a second input receiving a reference signal and an output providing an analog output signal defined by an amplified representation of the analog input signal and a dc offset component corresponding to the reference signal is combined with feedback circuitry for minimizing variations in the dc offset component of the analog output signal. The feedback circuitry comprises a counter circuit having a count value associated therewith, a first input receiving the analog output signal, a second input receiving the reference signal and an output connected to the first input of the analog signal amplifier circuit. The counter circuit periodically changes the count value in a first direction when the analog output signal exceeds the reference signal and periodically changes the count value in a second opposite direction when the reference signal exceeds the analog output signal. The counter circuit provides an analog feedback signal at the counter circuit output proportional to the count value, wherein the analog feedback signal minimizes variations in the dc offset component of the analog output signal by compensating for variations in the dc offset component of the analog input signal.
One object of the present invention is to provide analog/digital feedback circuitry for minimizing dc offset variations in an analog output signal of a gain circuit having an input receiving an analog input signal defined by an ac signal component due to a driving force and a dc offset component independent of the driving force.
Another object of the present invention is to provide such feedback circuitry that eliminates the need for any external componentry.
Yet another object of the present invention is to provide an analog signal gain circuit having an input receiving an analog input signal defined by an ac signal component due to a driving force and a dc offset component independent of the driving force wherein variations in the dc offset component of the analog output signal of the gain circuit are minimized.
Still another object of the present invention is to provide such an analog signal gain circuit as a single integrated circuit.
These and other objects of the present invention will become more apparent from the following description of the preferred embodiment.